DocumentCode
438436
Title
Low-power techniques for network security processors
Author
You, Yi-Ping ; Tseng, Chun-Yen ; Huang, Yu-Hui ; Huang, Po-Chiun ; Hwang, TingTing ; Hsu, Sheng-Yu
Author_Institution
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume
1
fYear
2005
fDate
18-21 Jan. 2005
Firstpage
355
Abstract
In this paper, we present several techniques for low-power design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and dual threshold voltage assignments, for network security processors. The experiments show that the proposed methods and designs provide the opportunity for network security processors to achieve the goals of both high performance and low power.
Keywords
integrated circuit design; low-power electronics; microprocessor chips; processor scheduling; security of data; dual threshold voltage assignments; dynamic voltage generator; low-power design; low-power scheduling algorithm; network security processors; Algorithm design and analysis; Computer networks; Cryptography; Data security; Information security; National security; Power generation; Power system security; Scheduling algorithm; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN
0-7803-8736-8
Type
conf
DOI
10.1109/ASPDAC.2005.1466188
Filename
1466188
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