Design and test of a scalable security processor

Author

Su, Chih-Pin ; Wang, Chen-Hsing ; Cheng, Kuo-Liang ; Huang, Chih-Tsun ; Wu, Cheng-Wen

Author_Institution

Dept. of Electr. Eng., National Tsing Hua Univ., Hsinchu, Taiwan

Volume

1

fYear

2005

fDate

18-21 Jan. 2005

Firstpage

372

Abstract

This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT platform is also implemented for the design-test integration. The security processor has been fabricated with 0.18μm CMOS technology. The core area is 3.899mm × 2.296mm (525K gates approximately) and the operating clock rate is 83MHz.

Keywords

CMOS integrated circuits; cryptography; design for testability; integrated circuit design; microprocessor chips; 0.18 micron; 83 MHz; CMOS technology; DFT platform; clock rate; crypto-DMA controller; crypto-engines; cryptographic processing; data channels; data gathering; data scattering; design-test integration; scalable security processor; security processing; Acceleration; CMOS process; CMOS technology; Costs; Cryptography; Data security; Energy consumption; Random number generation; Scattering; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific

Print_ISBN

0-7803-8736-8

Type

conf

DOI

10.1109/ASPDAC.2005.1466191

Filename

1466191