DocumentCode
438444
Title
Optimal redistribution of white space for wire length minimization
Author
Tang, Xiaoping ; Tian, Ruiqi ; Wong, Martin D F
Author_Institution
IBM T.J. Watson Res., New York, NY, USA
Volume
1
fYear
2005
fDate
18-21 Jan. 2005
Firstpage
412
Abstract
Existing floorplanning algorithms compact blocks to the left and bottom. Although the compaction obtains an optimal area it may not be good to meet other objectives such as minimizing total wire length which is the first-order objective. It is not known in the literature how to place blocks to obtain an optimal wire length. In this paper, we first show that the problem can be formulated as linear programming. Thereafter, instead of using the general but slow linear programming, we propose an efficient min-cost flow based approach to solve it. Our approach guarantees to obtain the minimum of total wire length in polynomial time and meanwhile keep the minimum area by distributing white space smarter for a given floorplan topology. We also show that the approach can be easily extended to handle constraints such as fixed-frame (fixed area), IO pins, pre-placed blocks, boundary blocks, range placement, alignment and abutment, rectilinear blocks, soft blocks, one-dimensional cluster placement, and bounded net delay, without loss of optimality. Practically, the algorithm is so efficient in that it finishes in less than 0.4 seconds for all MCNC benchmarks of block placement. It is also very effective. Experimental results show we can improve 4.2% of wire length even on very compact floorplans. Thus it provides an ideal way of post-floorplanning (refine floorplanning).
Keywords
circuit optimisation; integrated circuit layout; linear programming; minimisation; 1D cluster placement; IO pins; block placement; boundary blocks; bounded net delay; fixed-frame constraint; floorplan topology; floorplanning algorithms; linear programming; pre-placed blocks; range placement; rectilinear blocks; soft blocks; white space redistribution; wire length minimization; Circuits; Compaction; Delay; Pins; Runtime; Timing; Topology; Very large scale integration; White spaces; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN
0-7803-8736-8
Type
conf
DOI
10.1109/ASPDAC.2005.1466198
Filename
1466198
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