Title :
Crowdedness-balanced multilevel partitioning for uniform resource utilization
Author :
Cheon, Yongseok ; Wong, Martin D F
Author_Institution :
Adv. Technol. Group, Synopsys Inc., Hillsboro, OR, USA
Abstract :
In this paper, we propose a new multi-objective multilevel K-way partitioning which is aware of resource utilization distribution, assuming the resource utilization for a partitioned block is proportional to the logic occupation and the interconnections required for the block. A new quality of the partitioning solution, crowdedness, is defined as a virtual complexity metric where the physical size and the local connectivity of a partitioned block are considered simultaneously in the form of a weighted sum. The partitioning solutions driven by overall cut quality minimization tend to have wide variances of local interconnections for different blocks. The difference of block sizes, combining with the variance of the interconnections, potentially leads to the significant imbalance of the crowdedness (equivalently. resource utilization), even though the feasibility imposed by a block-size constraint is satisfied. Using the crowdedness metric, we explore the new partitioning solution space where the local interconnections are adaptively adjusted according to the block sizes, still under the same objective of overall interconnections minimization. By the carefully designed prioritized cell move policy, the proposed crowdedness-based partitioning achieves near-optimal solutions in terms of resource utilization distribution, while the overall interconnection quality also is improved but the feasibility is barely violated. The proposed approach is practically beneficial to multi-FPGA applications, in which excessive interconnections for a FPGA generate additional logics inside of the FPGA.
Keywords :
circuit optimisation; field programmable gate arrays; integrated circuit interconnections; integrated circuit layout; logic partitioning; block-size constraint; crowdedness balanced multilevel partitioning; cut quality minimization; interconnections minimization; local connectivity; logic occupation; multi-FPGA applications; partitioned block; resource utilization distribution; uniform resource utilization; virtual complexity metric; Costs; Field programmable gate arrays; Integrated circuit interconnections; Joining processes; Logic; Mice; Minimization; Resource management; Routing;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466199