DocumentCode :
438446
Title :
PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits
Author :
Hwang, Chanseok ; Pedram, Massoud
Author_Institution :
Dept. of Electr. Eng.-Syst., Southern California Univ., Los Angeles, CA, USA
Volume :
1
fYear :
2005
fDate :
18-21 Jan. 2005
Firstpage :
428
Abstract :
In this paper, we present a new performance-driven multilevel partitioning algorithm, which calculates the timing gain of a move in the move-based partitioning strategies based on the aggregation of preferred signal directions. In addition, we propose a new timing-aware multilevel clustering algorithm that uses the connection strength of an edge as the primary objective, and the maximum depth or the maximum hop-count of any path containing the edge as a tiebreaker for the clustering step. These ideas are integrated into a general multilevel partitioning framework, which consists of three phases: uncoarsening, initial partitioning, and coarsening and refinement phases. The benchmarks show that, on average, we can reduce delay by 14.6%, while increasing the cutsize by 1.2% when compared to hMetis (Karygpis et al., 1997).
Keywords :
integrated circuit layout; logic partitioning; pattern clustering; I/O conduits; coarsening phase; connection strength; initial partitioning phase; maximum depth; maximum hop-count; move-based partitioning strategy; performance-driven multilevel partitioning; preferred signal direction aggregation; refinement phase; timing-aware multilevel clustering algorithm; uncoarsening phase; Circuit analysis; Clustering algorithms; Delay effects; Logic circuits; Partitioning algorithms; Performance gain; Portable media players; Runtime; Signal processing; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
Type :
conf
DOI :
10.1109/ASPDAC.2005.1466201
Filename :
1466201
Link To Document :
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