DocumentCode
438466
Title
A variation-aware low-power coding methodology for tightly coupled buses
Author
Muroyama, Masanori ; Tarumi, Kosuke ; Makiyama, Koji ; Yasuura, Hiroto
Author_Institution
Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
Volume
1
fYear
2005
fDate
18-21 Jan. 2005
Firstpage
557
Abstract
This paper describes a novel low-power coding methodology for buses. Ultra deep submicron technology and system-on-chip have resulted in a considerable portion of power consumption on buses, in which the major sources of the power consumption are the transition activities on the signal lines and the coupling capacitances of the lines. In addition, we enter an era of considering variation of the effective coupling capacitances. We address power reduction including these phenomena by using variable length coding. Experimental results show the effectiveness of our methodology.
Keywords
ULSI; integrated circuit design; low-power electronics; system buses; system-on-chip; variable length codes; coupling capacitance; power consumption; power reduction; signal lines; system-on-chip; tightly coupled bus; ultra deep submicron technology; variable length coding; variation-aware low-power coding methodology; Capacitance; Computer science; Costs; Coupling circuits; Delay effects; Delay estimation; Encoding; Energy consumption; Power engineering and energy; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN
0-7803-8736-8
Type
conf
DOI
10.1109/ASPDAC.2005.1466226
Filename
1466226
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