Implementation of a 5 × 5 trits multiplier in a quasi-adiabatic ternary CMOS logic

Adiabatic switching is one technique to design low power digital IC. In order to diminish its expensive silicon area requirements an adiabatic ternary logic is proposed. A 5×5 trits (ternary signals) multiplier has been designed and implemented using this logic in a 0.7µm CMOS technology. Results show a satisfactory power saving and a decreasing of the area needed with respect to an adiabatic binary one.