CMOS circuit technique for serial IC interconnection up to 1.1 Gb/s

CMOS circuits for asynchronous data transmission are descibed, designed for low power transmission at data rates up to 1.1 Gb/s. The proposed transmission system consists of a current source transmitter, a receiver for low swing operation including constant active termination (CAT) for matched line-impedance, and a clock recovery PLL for serial NRZ data. Data recovery is possible between 720 Mb/s and 1.1 Gb/s for pseudo-noise test patterns up to length (2³¹-1) bit. The complete serial data transmission system consumes about 87 mW (3.3 V) including PLL at 1.1 Gb/s.