A robust analogue interface system for sub-micron CMOS video DSP

This paper describes the front-end architecture for a fully integrated low voltage CMOS video DSP function, including AGC, equalisation, clamping, sync and A/D conversion. Attention is paid to minimising the influence of substrate and power supply noise despite a large digital part with differing clock domains. The system maximises the available dynamic range in the 3.3V supply, with several high bandwidth rail-to-rail functions. A novel arrangement with high noise immunity level estimators is used to clamp the video in the middle of the dynamic range of the AGC input, hence minimising the amplification of unwanted DC components. Extensive mixed signal test facilities are also included in the design. The chip is fabricated in 0.5µ CMOS, and operates from a single 3.3V supply.