Hierarchical N-port memory architecture based on 1-port memory cells

The new hierarchical N-port memory architecture features parallel read/write access with low access conflict probability from all ports, although only 1-port memory cells are used. A simple, effective circuit is proposed for conflict handling and monitoring. In comparison with conventional implementation of all N ports in each memory cell, substantial memory area reductions between 28% (2 ports) and 68% (16 ports) can be realized, while access times are nearly equivalent. The architecture is a generalization of the previous state of the art and is applicable for all types of dynamic, static and non-volatile memory.