Digital goes analog

If we continue to increase the complexity of ICs at the same pace as we did from 1960 onwards, this complexity will have reached a level of half a billion transistors per chip, within a decade from now. And the clock period is ´expected´ to be well below the one nanosecond. Even if we don´t believe these excessive numbers, design styles and methods need to be changed to fully exploit the potentials of IC complexity and performance, as predicted by the Semiconductor Industrial Association (SIA) roadmap. In this paper the consequences for deep-submicron IC design will be discussed, with focus on future trends of power, speed, reliability and signal integrity. The increasing dominance of physical effects that create interference and noise in VLSI designs, more and more requires analog measures to limit their influence.