DocumentCode
439272
Title
A 16 mW, 120 dB linear switched-capacitor delta-sigma modulator with dynamic biasing
Author
Kasha, Dan B. ; Lee, Wai L. ; Thomsen, Axel
Author_Institution
Cirrus Logic Inc., Austin, TX
fYear
1998
fDate
22-24 Sept. 1998
Firstpage
160
Lastpage
163
Abstract
A high resolution fourth-order ΔΣ ADC is presented. Power reduction techniques have been applied across many aspects of the design. A class-A amplifier was designed with bias currents optimized according to the expected activity in each clock phase. The modulator achieves a 122dB dynamic range over a 400Hz bandwidth, -123dB THD, and 16mW power consumption from a single 5V supply. It is implemented in a 0.6µm double polysilicon CMOS process, and has an active area of 2 mm2.
Keywords
Bandwidth; Capacitors; Circuit noise; Delta modulation; Design optimization; Logic; Nonlinear distortion; Sampling methods; Signal to noise ratio; Stability;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1998. ESSCIRC '98. Proceedings of the 24th European
Type
conf
DOI
10.1109/ESSCIR.1998.186233
Filename
1470990
Link To Document