• DocumentCode
    439276
  • Title

    A real-time digital VCR encode/decode and MPEG2 decode LSI implemented on a dual-issue RISC processor

  • Author

    Mohri, A. ; Yamada, A. ; Yoshida, T. ; Sato, H. ; Takata, H. ; Nakakimura, K. ; Tsuchihashi, K. ; Shimotsuma, Y.

  • Author_Institution
    Mitsubishi Electric Corporation, Hyogo, Japan
  • fYear
    1998
  • fDate
    22-24 Sept. 1998
  • Firstpage
    176
  • Lastpage
    179
  • Abstract
    A real-time system LSI for Digital VCR (DVCR) encoding/decoding and MPEG2 decoding is implemented on a dual-issue RISC processor (DRISC) with dedicated hardware for variable length coding/decoding and video-block loading. The DRISC achieves 972MOPS and supports multiple standards with the block-level dedicated processing. The LSI size is 7.7×7.2mm2in a 0.25-µm process.
  • Keywords
    Decoding; Discrete cosine transforms; Encoding; Filters; Hardware; Large scale integration; Quantization; Reduced instruction set computing; Video compression; Video recording;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1998. ESSCIRC '98. Proceedings of the 24th European
  • Type

    conf

  • DOI
    10.1109/ESSCIR.1998.186237
  • Filename
    1470994
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439276