A 1.0V 180Mhz 85 µ W/Mhz 8k × 16b SRAM in a standard 0.25 µm CMOS

A low voltage embedded single port memory implemented in a 6 metals, 0.25µm standard CMOS process is described. The chip is achieving 180Mhz maximum frequency, with a 4.2ns access time at 1V and 25°C. The hierarchical wordline architecture, and a differential output bus allow low power characteristics, at the same time high speed is reached, especially thanks to a novel dynamic wordline decoder.