Low power SOI CMOS multipliers : 2D vs. 3D

In this paper a new three-dimensional SOI on SOI technology is presented, then design methodologies are proposed for this technology and last, a comparison is carried out between 2D and 3D designs. Here, the P-channel devices are stacked over the N-channel ones. All gates are 0.1µm length. New design constraints are introduced. Consequently, new design methodologies and tools have to be developed in order to take advantage of the reduced length of interconnections. A 16×16 bit multiplier was designed in this technology. Comparative results between 2D and 3D integration are given in terms of energy consumption, performance, delay and area.