DocumentCode
439295
Title
A 10b 50-msample/s CMOS ADC in ASIC process
Author
Wada, A. ; Kuniyuki Tani ; Kato, K. ; Shimizu, H.
Author_Institution
Sanyo Co., Ltd.
fYear
1998
fDate
22-24 Sept. 1998
Firstpage
252
Lastpage
255
Abstract
We have developed a 2-step interstage amplifying pipeline system and new circuit technologies for residue amplifiers. With these techniques, we developed a 50 Msample/s 10b CMOS ADC with a 3.3V power supply, In 0.35µm 1-poly 2-Metal ASIC process without a special analog process. This CMOS ADC measures 4.84mm2. The first test chip was fabricated to verify the new architecture and was measured. It shows good linearity of less than ±1LSB and 130mW power consumption at 50MHz sampling.
Keywords
Application specific integrated circuits; CMOS process; CMOS technology; Circuit testing; Energy consumption; Linearity; Pipelines; Power supplies; Sampling methods; Semiconductor device measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1998. ESSCIRC '98. Proceedings of the 24th European
Conference_Location
The Hague, The Netherlands
Type
conf
DOI
10.1109/ESSCIR.1998.186256
Filename
1471013
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