DocumentCode
439305
Title
An analog beam-forming circuit using switched-current delay lines
Author
Stefanelli, B. ; O´Connor, I. ; Quiquerez, L. ; Kaiser, A. ; Billet, D.
Author_Institution
IEMN - ISEN, Lille, France
fYear
1998
fDate
22-24 Sept. 1998
Firstpage
300
Lastpage
303
Abstract
1120 analog memory points on a 0.8mm CMOS chip are arranged in 16 independent fully programmable delay lines. At the nominal 64MHz sampling rate, harmonic distortion is -48dB, dynamic range above 60dB and power consumption is 1.22W from a single 5V supply. The die area is 72mm2.
Keywords
Clocks; Delay lines; Dynamic programming; Focusing; Impedance; Probes; Signal restoration; Signal sampling; Switching circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1998. ESSCIRC '98. Proceedings of the 24th European
Conference_Location
The Hague, The Netherlands
Type
conf
DOI
10.1109/ESSCIR.1998.186268
Filename
1471025
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