• DocumentCode
    439319
  • Title

    A 155 Mbit/s fully digital bit synchronizer

  • Author

    Burzio, Marco ; Pellegrino, Paolo

  • Author_Institution
    CSELT Centro Studi e Laboratori Telecommunicazioni, Torino, Italy
  • fYear
    1998
  • fDate
    22-24 Sept. 1998
  • Firstpage
    356
  • Lastpage
    359
  • Abstract
    In this paper we describe a circuit operating at 155 Mbit/s for the alignment of a clock to a continuos or bursty data flow. Possible drifts, jitter and wander are taken into account. The alignment method allows a fully digital implementation, with a reduced cost and high speed performance in line with common telecom specifications (ATM, SDH). The circuit has been realized in a 0.45µm CMOS Gate Array technology.
  • Keywords
    CMOS technology; Circuits; Clocks; Costs; Jitter; Phase locked loops; Phased arrays; Synchronization; Synchronous digital hierarchy; Telecommunications;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1998. ESSCIRC '98. Proceedings of the 24th European
  • Type

    conf

  • DOI
    10.1109/ESSCIR.1998.186282
  • Filename
    1471039
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439319