Area-efficient multiport memories for the Tb/s bandwidth era

Tb/s memory-access bandwidth becomes conceivable, if N>30 ports with parallel access capability are available. Conventional multiport-memory architectures cannot realize such memories efficiently, because memory-cell area explodes due to quadratic area increase with N. 32- port-memory cells e. g. are estimated factors 80 (SRAM, large 1-port cell) and 400 (ROM, small 1-port cell) larger than correspondng 1-port cells. A recently proposed hierarchical architecture [1] can reduce this unacceptable area consumption to a small fraction, because the smallest unit-size with N-port capability is increased by using blocks of 1-port-cells. Possible area reductions become larger with increasing port number and storage capacity. For hierarchical 32-port SRAMs with storage capacities >6Mb enormous reductions to area-fractions <1/20 of the conventional architecture are estimated on the basis of design data. Since high clock frequencies can be achieved with pipeline concepts, Tb/s bandwidth VLSI systems become already a realistic perspective with today´s advanced CMOS technologies.