A low-power truly-modular 1.8GHz programmable divider in standard CMOS technology

We present a modular and scalable divider architecture that is especially suited for low power applications. The implementation of the divider cells in SCL is described, and a new design method for power dissipation optimization, based on an AC simulation technique, is introduced. An 18bit implementation of the architecture in a conservative 0.35µm bulk CMOS technology is described, which achieved state-of-the-art power efficiency and input sensitivity for CMOS silicon technologies.