A dynamically controllable DC/DC level converter and its application to high-speed, low-power circuits

A new DC/DC level converter has been developed for use in high-speed, low-power circuits. The level converter can increase the DC voltage which is supplied to an active-load circuit on request, or supply a minimal DC voltage to a load circuit in the stand-by mode. 32-word register files and 512-bit cache SRAMs were developed using 0.25-µm HEMT technology to examine the effectiveness of the DC/DC level converter in power reduction. Experimental results showed that the power dissipation P of the 32-word register file with on-chip DC/DC level converters was 1.04 W, a reduction to 57.1% of that of an equivalent conventional register file, while the operating frequency fc was 6.42 GHz that is 92.9% of fcfor the conventional register file. P for the 512-bit cache SRAM with the new DC/DC level converters was 34.3 mW, 89.7% of the value for an equivalent conventional cache SRAM, with the read-access time of 455 psec, only 1.1% longer than that of the conventional cache SRAM. The DC/DC level converter technology is also useful in that it reduces P due to subthreshold currents in CMOS and pass-transistor logic circuits.