DocumentCode
439491
Title
SOI CMOS circuit design exposed - Another dirty tricks campaign?
Author
Redman-White, B. ; Bernstein, K.
Author_Institution
Philips Semiconductors, UK & Southampton University, UK
fYear
2000
fDate
19-21 Sept. 2000
Firstpage
141
Lastpage
151
Abstract
The SOI CMOS is now shaking off the double-edge epithet of the "technology of tomorrow" and emerging as a viable mainstream process. Much has been written about the device physics, but rather little definitive material has addressed circuit designers\´ questions. What has gained attention have been arguments over achievable benefits, and scary stories of strange behaviour, with great difficulties in design and simulation. In this paper we aim to put the technology issues in perspective for the designer, and to show where the opportunities as well as the problems lie. To solve these problems and get the benefits of SOI we focus not on technology tweaks, but on the circuit designers\´ stock in trade - (dirty) tricks.
Keywords
CMOS process; CMOS technology; Capacitance; Circuit simulation; Circuit synthesis; Error analysis; Latches; MOSFET circuits; Physics; Semiconductor materials;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European
Conference_Location
Stockholm, Sweden
Type
conf
Filename
1471233
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