A 350 MHz programmable analog FIR filter using mixed-signal multiplier

This paper describes a programmable analog FIR filter, which uses a new mixed-signal multiplier technique for directly multiplying the digital filter coefficients and the analog input signals. A 6-tap prototype design was design and fabricated in a 0.5 µm CMOS process. The active area is less than 1.1 × 1.1 mm². The FIR filter operates up to 360 MS/s and dissipates less than 160 mW for a 3.3 V supply. The THD was measured to be -41 dB for a 1 V peak-to-peak, 25.7 MHz input signal.