• DocumentCode
    439497
  • Title

    A low-power 14-b 5 MS/s CMOS pipeline ADC with background analog self-calibration

  • Author

    Goes, J. ; Vital, J.C. ; Alves, L. ; Ferreira, N. ; Ventura, P. ; Bach, E. ; Franca, J.E. ; Koch, R.

  • Author_Institution
    Instituto Superior Técnico, Lisboa Codex, Portugal
  • fYear
    2000
  • fDate
    19-21 Sept. 2000
  • Firstpage
    172
  • Lastpage
    175
  • Abstract
    This paper presents a low-power 14-b 5 MS/s area-optimized pipelined ADC with background analog self-calibration. Measured results from the prototypes fabricated in a 0.6 µm 5 V DPDM CMOS technology show 13.5-b DNL, 12-b INL, 80 dB SFDR and 76 dB SNDR. The core area is 10mm2and it dissipates less than 145mW at 5V.
  • Keywords
    CMOS technology; Communication systems; Electronic switching systems; Integrated circuit noise; Pipelines; Postal services; Power dissipation; Prototypes; Read only memory; Signal resolution;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European
  • Conference_Location
    Stockholm, Sweden
  • Type

    conf

  • Filename
    1471239
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439497