A dual-phase-controlled dynamic latched (DDL) amplifier for high-speed and low-power DRAMs

A dual-phase-controlled dynamic latched (DDL) amplifier for a differential data transfer scheme designed to simultaneously achieve high-speed and low-power DRAMs is described. This circuit reduces the excessive operating margin caused by the device fluctuation by using a pair of dynamic latched amplifiers, controlled by a dual-phase clock, to automatically correct the output data. Two circuit technologies are used in the DDL amplifier to achieve a 200 MHz operation in a 1-Gb SDRAM: a cycle-time-progressive control technique that reduces the clock-cycle time, and a shared DDL amplifier technique that reduces the area penalty of the DDL amplifier. They reduce the access time to 10 ns, which is 1.2-ns less than the conventional dynamic amplifier, while also reducing the operating current to less than 10% that of the static amplifier.