A low power reconfigurable I/O DRAM macro with single bit line writing scheme

A novel bit line control scheme, Single Bit line Writing Scheme, is proposed for low power DRAM. The suggested control scheme, which is applied to the folded bit line and shared sense amplifier structure, suppresses the voltage swing of unnecessary bit line. By this scheme, the power consumption occurred during bit line sensing is reduced by 22% with negligible area penalty. In order to provide I/O reconfigurability, a flexible I/O scheme is also proposed. From the widest I/O configuration, using an I/O decoder and a 4-to-1 multiplexer, I/O width can be reduced 1/4 of currently used I/O width. Low power DRAM Macros are designed for a frame buffer with 0.18µm embedded DRAM technology.