A 12 GHz/128 frequency divider in 0.25 µm CMOS

A 12 GHz divide-by-128 frequency divider has been implemented in a first generation 0.25µm CMOS technology. High-speed divide-by-two flipflops have been developed, that are not only optimised for high frequency operation but also for driving the cascade of flipflops that form the divide-by-128 divider. An operating frequency of 12 GHz is achieved with a power consumption of 60 mW. In divide-by-16 operation mode, the maximum operating frequency is as high as 14 GHz. All measurements are performed without using RF probes nor flip-chip bonding.