A 2GHz low-distortion low-noise two-stage LNA employing low-impedance bias terminations and optimum inter-stage match for linearity

A two-stage stacked high IIP3 LNA with low current consumption is presented. Low-impedance bias terminations and optimum inter-stage match are used for IIP3 enhancement. A new graphical design technique is introduced for optimising the linearity trade-offs in two-stage amplifiers and for optimising the on-chip interstage matching network. Also, novel active circuits for bias modulation suppression are discussed. The LNA has been fabricated in a commercial SiGe BiCMOS technology, and measurement results are presented.