• DocumentCode
    439543
  • Title

    Source-pulsed dynamic-threshold CMOS SRAMs for fast, portable applications

  • Author

    Bhavnagarwala, A.J. ; Kapoor, A. ; Meindl, J.D.

  • Author_Institution
    Georgia Institute of Technology, Atlanta, GA
  • fYear
    2000
  • fDate
    19-21 Sept. 2000
  • Firstpage
    360
  • Lastpage
    363
  • Abstract
    A novel quad-rail CMOS SRAM cell architecture that doubles cell read current, improves cell static noise margin (SNM) by 70%, increases cell immunity to SER, and lowers cell standby power by over an order of magnitude is proposed. These improvements over conventional 6T CMOS SRAM cells, verified with HSPICE simulations on a 0.18µm industrial process are achieved by implementing a scheme of WL transition triggered pulses on power, ground and substrate terminals of cell transistors that share a common WL.
  • Keywords
    Boosting; CMOS process; CMOS technology; Circuit stability; Electrical capacitance tomography; Geometry; MOSFET circuits; Random access memory; Threshold voltage; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European
  • Conference_Location
    Stockholm, Sweden
  • Type

    conf

  • Filename
    1471286
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439543