• DocumentCode
    439547
  • Title

    Dynamic flip-flop with improved power

  • Author

    Nedovic, Nikola ; Oklobdzija, Vojin G.

  • Author_Institution
    University of California, Davis, CA
  • fYear
    2000
  • fDate
    19-21 Sept. 2000
  • Firstpage
    376
  • Lastpage
    379
  • Abstract
    An improved design of a dynamic Flip-Flop is presented. Proposed design overcomes the problem of the glitch at the output and improves Power-Delay Product for about 10%, while preserving logic embedding property. This is accomplished by equalizing the tpLHand tpHLof the flip-flop and careful design of keeper elements in the circuit. New design introduces insignificant area increase.
  • Keywords
    Circuit topology; Clocks; Delay effects; Energy consumption; Flip-flops; Inverters; Latches; Logic circuits; Logic design; Logic devices;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European
  • Conference_Location
    Stockholm, Sweden
  • Type

    conf

  • Filename
    1471290
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439547