• DocumentCode
    439559
  • Title

    A 1.8V 20mW 1mm214b 100Msample/s CMOS DAC

  • Author

    Tiilikainen, Mika

  • Author_Institution
    Nokia Mobile Phones, Helsinki, Finland
  • fYear
    2000
  • fDate
    19-21 Sept. 2000
  • Firstpage
    435
  • Lastpage
    438
  • Abstract
    A binary weighted current steering DAC is a power-efficient architecture, because almost all the current taken from the supply is used for the output signal. Typically, the architecture suffers from poor linearity characteristics, but the problem can be prevented with a new calibration method, where the currents generated for the most-significant bits are fine-tuned. As a result, a very compact and low-power solution can be implemented by using a low-voltage digital technology.
  • Keywords
    Calibration; Character generation; Circuit topology; Complexity theory; Linearity; MOSFET circuits; Mobile handsets; Read only memory; Temperature; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European
  • Conference_Location
    Stockholm, Sweden
  • Type

    conf

  • Filename
    1471303
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439559