An image-reject downconverter with sideband selection for double-conversion receiver

An image-reject downconverter unit for a double-conversion receiver is presented. The circuit includes a LNA, image-reject mixers in Hartley configuration, a 3- stage polyphase filter, an IF-amplifier and a novel SAW driver. For LO generation the circuit includes a 6-GHz on-chip VCO, a divide-by-four circuit for quadrature LO and divide-by-16 for feeding an external PLL. Signal reversal switching in the LO buffer can be used for altering the location of image frequency. The circuit features 44-dB gain, 40-dB image rejection, 4.6-dB noise figure, 20-dBm OIP3 and it is fabricated in a 0.9- µm SiGe HBT technology.