A CMOS voltage reference based on weighted difference of gate-source voltages between PMOS and NMOS transistors for low dropout regulators

A CMOS voltage reference, which takes advantage of weighted difference of the gate-source voltages between a PMOS and an NMOS transistor operating in saturation region, is presented in this paper. The reference has been implemented in a standard 0.6-µm CMOS process (Vthn≈ |Vthp| ≈ 0.9 V@0° C) and gives a temperature coefficient of not greater than 62 ppm/°C from 0 to 100° C without trimming, while consuming a maximum of 9.7 µA with a minimum supply of 1.4 V. The worst-case line regulation is ±0.17 %/V. The occupied chip area is 0.055 mm². The proposed reference has been applied to a 10-mA CMOS low dropout regulator, and a temperature coefficient of 94 ppm/°C is achieved when the regulator delivers maximum load current.