ACE16K: An advanced focal-plane analog programmable array processor

This paper presents a new generation 128×128 Focal-Plane Analog Programmable Array Processor (FP-APAP), from a system level perspective. It has been manufactured in a 0.35µm standard digital 1P-5M CMOS Technology. The chip has been designed to achieve the high-speed and moderate-accuracy (∼8bits) requirements of most real time image processing applications. It has been designed to be easily embedded in conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four millions transistors, 80% of them working in analog mode, and exhibits a relatively low power consumption (<4W, i.e. less than 1µW per transistor). Computing vs. power peak values are in the order of 1TeraOPS/W, while maintained VGA (640×480)processing throughputs of 100Frames/s are possible with about 10-20 basic image processing tasks on each frame.