A low-power CMOS silicon retina for feature extraction in real-time, embedded systems

A standard CMOS silicon retina for the acquisition and processing of images is presented. Feature extraction and edge enhancement are obtained through 1-D Gabor convolutions. Low-power (1µW per pixel) and real-time (less than 20 µsec for complete processing) operations make this device suitable for embedded smart vision systems. Such performances are obtained by means of analog, collective circuits surrounding the active sensors. Test measurements of the first VLSI prototype show a very good matching with expected performances.