High-speed CMOS analog Viterbi detector for 4-PAM partial response signalling

A high-speed analog Viterbi detector based on 4-PAM duobinary scheme is designed and implemented in a 0.25 µm CMOS process. This chip is the first analog integrated implementation of a reduced state sequence detector. Due to test equipment limitations, experimental results are given for 200 Mb/s operation while simulation results indicate a speed of 1 Gb/s. Power dissipation is 60 mW from a 2.5V supply.