Noise-constrained design of reliable power networks for mixed-power supply systems

Electrostatic discharge (ESD) accounts for over 30% chip failure that occurs during VLSI chip manufacturing. On-chip ESD network should be able to withstand the heating effects, sink the large currents during the ESD event and not be damaged by the ensuing high electric fields. The ways focused on ESD reliability may cause noise isolation concern among multiple power supplies. Our experimental results show that the noise coupled through ESD networks significantly degrades the performance of mixed-signal systems. This coupling noise cannot be easily suppressed because reducing the noise usually leads to the degradation of ESD performance. This paper presents a new method for designing noise-constrained ESD networks while improving the reliability. This idea features a common electrostatic discharge line (CEDL) with utilizing the estimation of maximum power/ground (PG) noise in digital circuits in the ESD network design. Experimental results demonstrate the potential for alleviating a tradeoff between ESD robustness and noise isolation in mixed-power supply networks.