A direct digital frequency synthesizer using a new ROM compression method

A new direct digital frequency synthesizer (DDFS) is proposed in this paper. It uses a new ROM compression method that divides each ROM in the conventional DDFS into two ROMs (a quantization ROM and an error ROM). The total size of the ROMs in the proposed DDFS is significantly reduced compared to the original ROM. The ROM compression ratio of 78 is achieved for a DDFS with 12bit output data. A DDFS with -86.9 dBc spectral purity and 12bit output data for sine function was implemented in a 0.35µm CMOS technology. The power dissipation is 9.56mW at 100MHz with 3.3V and the maximum operating clock frequency is 500MHz.