DocumentCode
439636
Title
0.13um 32Mb/64Mb embedded DRAM core with high efficient redundancy and enhanced testability
Author
Kikukawa, Hirohito ; Tomishima, Shigeki ; Tsuji, Takaharu ; Kawasaki, Toshiaki ; Sakamoto, Shouji ; Ishikawa, Masatoshi ; Abe, Wataru ; Tanizaki, Hiroaki ; Kato, Hiroshi ; Uchikoba, Toshitaka ; Inokuchi, Toshihiro ; Senoh, Manabu ; Fukushima, Yoshifumi ;
Author_Institution
Matsushita Electric Industrial Co., Ltd., Kyoto, Japan
fYear
2001
fDate
18-20 Sept. 2001
Firstpage
281
Lastpage
284
Abstract
This paper describes the 32Mb and the 64Mb embedded DRAM core with high efficient redundancy, which is fabricated using 0.13µm triple-well 4-level Cu embedded DRAM technology. The core size of 18.9mm2and the cell efficiency of 51.3% for the 32Mb capacity, the core size of 33.4mm2and the cell efficiency of 58.1% for the 64Mb capacity are realized. This core can be achieved 230MHz burst access at 1.0V power supply condition adopting data bus architecture merged shift column redundancy. We implemented 4 test functions to improve the testability of embedded DRAM core. It realizes DRAM core test in a logic test environment.
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2001. ESSCIRC 2001. Proceedings of the 27th European
Conference_Location
Villach, Austria
Type
conf
Filename
1471388
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