Power saving in CMOS using a half-swing clocking scheme

In order to reduce power consumption, a half-swing clocking scheme is introduced in a complementary 4-phase clock system. Investigations of the latch behaviour at half-swing clock shows the suitability of C²MOS latches and transmission-gates. The increased latch delay is compensated by a resizing of the latch transistors and a higher internal supply voltage, due to the reduced voltage drop across the power supply network. The half-swing clocking scheme has been implemented in a representative layout section of a processor for real-time image processing. Power saving of 55% in the clock system has been achieved.