Evaluation of skew tolerance in delayed clocking scheme for dynamic circuits

We evaluate the skew tolerance in delayed clock distribution scheme for high speed dynamic circuits. The expression for clock skew tolerance is derived based on various timing constraints. The influence of duty cycle and timing of delayed clocks on skew tolerance is analysed. The design issues involved in the implementation of the delayed clocking scheme are discussed. A 410ps 64-bit parallel adder in 100 nm CMOS process technology is designed with high skew tolerance and low design cost.