Configurable area-IO memory for system-in-a-package (SiP)

System-in-a-Package (SiP), a generalization of System-on-a-Chip (SoC), provides a cost-effective solution for large-scale memory/logic integration. However, commercial memory chips are not optimized for SiP. Conventional IO design barriers the memory performance in SiP module. Furthermore, memory for SiP could be configurable to meet the bandwidth requirement for various logic architectures. This paper presents a configurable area-IO memory architecture, which can trade off the memory depth and word-width for different logic chips integrated with this memory module. A 512K SRAM chip has been designed to verify this approach.