A 30 MHz DDS clock generator with 8-bit, 130 ps delay generator and -50 dBc spurious level

A 30 MHz DDS clock generator circuit with time domain interpolation and-50 dBc spurious signal level has been designed. The sine look-up-table and D/A converter of the conventional DDS are replaced by a three-step digitally programmable delay generator with 130 ps resolution and 100 ps INL. This increases the effective sampling frequency to 7.68 GHz, so that no reconstruction filter is needed to create output square wave clock signal in the range of 0-15 MHz. The core size of the 0.35µm CMOS circuit is 0.3 mm²and it consumes 5-10 mA from a single 2.8 V supply.