DocumentCode :
439726
Title :
Design of a 3D fully-depleted SOI computational RAM
Author :
Koob, John C. ; Sung, Raymond J. ; Brandon, Tyler L. ; Elliott, Duncan G. ; Cockburn, Bruce F. ; McIlrath, Lisa
Author_Institution :
University of Alberta, Edmonton, Canada
fYear :
2002
fDate :
24-26 Sept. 2002
Firstpage :
135
Lastpage :
138
Abstract :
We present a three-dimensional processor-in-memory integrated circuit that provides linearly increasing processing power, while incurring no extra design effort or mask sets as the number of stacked dies increases. Innovative techniques for processor/memory redundancy and fast global bus evaluation are described. The test chip, with 128 kb of memory and 512 processing elements on two fully-depleted silicon-on-insulator dies, can achieve 170 billion bit-operations per second at 400 MHz.
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European
Conference_Location :
Florence, Italy
Type :
conf
Filename :
1471484
Link To Document :
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