A slew rate controlled output driver using PLL as compensation circuit

A slew rate controlled output driver adopting delay compensation method is implemented using 0.18 µm CMOS process for storage device interface. Phase-Locked Loop is used to generate compensation current and constant delay time. Compensation current reduces the slew rate variation over process, voltage and temperature variation in output driver. To generate constant delay time, the replica of VCO in PLL is used in output driver´s slew rate control block. That reduces the slew rate variation over load capacitance variation. That has less 25% variation at slew rate than that of conventional output driver. The proposed output driver can satisfy UDMA100 interface which specify load capacitance as 15 ∼ 40pF and slew rate as 0.4 ∼ 1.0[V/ns].