• DocumentCode
    439751
  • Title

    A CMOS 7-Gb/s power-efficient 4-PAM transmitter

  • Author

    Farzan, K. ; Johns, D.A.

  • Author_Institution
    University of Toronto, Toronto, ON, Canada
  • fYear
    2002
  • fDate
    24-26 Sept. 2002
  • Firstpage
    235
  • Lastpage
    238
  • Abstract
    A novel power-efficient architecture for a multi-level PAM transmitter is proposed. A data look ahead technique is used to pre-switch the current sources so that drive current is reduced when transmitting small voltage levels. Interestingly, this transmitting small voltage need for a pre-driver block which also saves transmitter power. Based on this architecture, a 4-PAM transmitter is designed in 0.18µm standard digital CMOS technology. The transmitter achieves 3.5GS/s (7Gb/s) and occupies 0.16mm2. The output driver and the entire transmitter consumed only 11.25mW and 66mW, respectively.
  • Keywords
    Bit error rate; CMOS technology; Driver circuits; Educational institutions; Intersymbol interference; Power dissipation; Power supplies; Tail; Transmitters; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European
  • Conference_Location
    Florence, Italy
  • Type

    conf

  • Filename
    1471509
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439751