An accurate estimation model for subthreshold CMOS SOI logic

A simple yet realistic physics-based model is introduced to describe the subthreshold drain current of a MOSFET taking into account the body-and drain-voltage dependencies, including the short channel effects. This model, verified by Spice simulations, describes adequately the pseudo-triode and pseudo-saturation regions of MOS transistors operated below VT. It can be applied for predicting bulk- or SOI CMOS circuit operation. Analytical expressions derived for the logic switching threshold and delay are applied to predict the performance of CMOS-SOI inverters.