DocumentCode
439790
Title
A low power symmetrically pulsed dual edge-triggered flip-flop
Author
Nedovic, N. ; Walker, W.W. ; Oklobdzija, V.G. ; Aleksic, M.
Author_Institution
Fujitsu Laboratories of America Inc., Sunnyvale, CA
fYear
2002
fDate
24-26 Sept. 2002
Firstpage
399
Lastpage
402
Abstract
A dual-edge triggered flip-flop suitable for low power applications is presented. HSPICE simulations conducted in 0.11u CMOS technology using 1.2V power supply voltage show that the proposed design is comparable in energy-delay product to high-performance single-edge triggered flip-flops while maintaining lower clock power. The Energy-Delay Product improvement of 14% and 50% smaller clock load compared to previously best published dual edge-triggered storage elements are demonstrated.
Keywords
CMOS technology; Clocks; Delay; Energy consumption; Flip-flops; Frequency; Laboratories; Pulse generation; Switches; Uncertainty;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European
Conference_Location
Florence, Italy
Type
conf
Filename
1471549
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