A self-controllable-voltage-level (SVL) circuit for low-power, high-speed CMOS circuits

A self-controllable-voltage-level (SVL) circuit--which can supply a maximum DC voltage to an active-load circuit on request or can decrease the DC voltage supplied to a load circuit in stand-by mode--was developed. This SVL circuit can drastically reduce stand-by leakage power of CMOS logic circuits with minimal overheads in terms of chip area and speed. Furthermore, it can also be applied to memories and registers, because such circuits fitted with SVL circuits can retain data even in the standby mode. The stand-by power of an 8-bit, 0.13µm CMOS adder with an on-chip SVL circuit is 11.7 nW, namely, 4.3% of that of an equivalent conventional adder, while the output signal delay is 790 psec, namely, only 3.8% longer than that of the equivalent conventional adder. Moreover, the stand-by power of a 512-bit memory cell array incorporating an SVL circuit for a 0.13-µm SRAM is 66.1 nW, 2.3% of that of an equivalent conventional memory-cell array. The read-access time of this 0.13-µm SRAM is 285 psec, that is, only 2 psec slower than that of the equivalent SRAM.