A sub-psec jitter PLL for clock generation in 0.12 µm digital CMOS

A fully integrated sub-psec jitter PLL realized in a standard digital 0.12µm CMOS copper technology with 1.5V supply is presented. A dual LC-VCO is implemented to support different standards for serial data transmission. We present the general concept and test chip results. Operating with a 311MHz reference clock the PLL achieves typ. 870fs integrated jitter, a phase noise of-115dBc/Hz @1MHz offset, on a 2.488GHz output with 45mW power and a module area of 0.7mm².